Application specific integrated circuit (ASIC) chip technology has undergone rapid changes in recent years. In this regard, present day ASIC chips are based on a core concept involving pre-designed models of complex functions that may serve a variety of applications. Thus, an ASIC chip cores in today's technology may well include controllers, interfaces, video circuitry, microprocessors and memory arrays. In short then, an ASIC chip is a system on a chip.
While such integrated circuit chips will have broad applications in emerging technologies, the complexity of such chips is far too complex and different from older integrated circuit technologies to permit such chips to be tested by older testing methodologies. In this regard, there have been several different methodologies for testing previous generation integrated circuit chips. Such methodologies have included IDDQ testing for determining physical chip defects such as bridging; RAMBIST or LRAM vector generation testing for determining memory functionality; full scan testing for verification of synchronous logic operations; and block or partitioning testing for determining mixed analog and digital signals circuits.
Each of the above mentioned methodologies require testing schemes based on random or pseudo-random vectors generated "off chip." In this regard, such testing is typically based on the conventional "line stuck-at-fault" model where test vectors are generated" off chip," applied and collected by means of automatic test equipment (ATE) and then analyzed for correctness by a workstation processing unit that applies specific algorithms and test programs.
While the above mentioned methodologies have been satisfactory for the older integrated circuit technologies, such methodologies are not entirely satisfactory for the highly complex integrated circuit of today. Therefore, it would be highly desirable to have a new and improved integrated circuit chip and method of testing such a chip, that greatly improves manufacturing throughput, substantially reduces manufacturing costs, and significantly reduces design verification time during the development process. Such a new and improved integrated circuit chip and method of testing it should not require the significant use of expensive automated test equipment or workstation processors.
Because of the problems associated with the older testing methodologies, newer testing approaches have been developed. One of the emerging technologies is known as the "built-in self test" or BIST approach. The BIST approach attempts to move certain portions of the semi-conductor test equipment located in the ATE onto the semiconductor base product to be tested. This approach reduces the complexity of the ATE, provides easier access to the embedded memories and other ASIC structures for testing purposes, and permits testing at full operational speeds.
While the BIST approach may be satisfactory for certain application, it is relatively expensive, requires a significant amount of space on the ASIC chip, and requires automated tools for integrating the BIST within the ASIC chip itself. Therefore, it would be highly desirable to have a new and improved ASIC chip that facilitates self testing to greatly reduce overall product development time and that has negligible overhead space on the ASIC chip itself.